Energy-Efficient Multiplier Design Using Urdhva Tiryagbhyam Algorithm and Approximate Compressors

Abstract

Efficient multiplier design is crucial for enhancing the performance of digital systems, particularly in applications requiring high-speed computations. This study focuses on implementing multipliers using the Vedic Urdhva Tiryagbhyam algorithm, incorporating approximate compressors for partial product addition in 5:3, 6:3, and 7:3 designs. The proposed method is compared with the existing method that employs stacker-based binary compressors. Both designs are synthesized and analyzed using the Xilinx Vivado tool, evaluating their performance based on area utilization (LUTs), static power, and dynamic power consumption. Experimental results reveal significant improvements in the proposed method. The area utilization is reduced from 596 LUTs to just 56 LUTs. Static power consumption drops from 0.823 W to 0.136 W, while dynamic power decreases from
48.008 W to 15.363 W. Overall, the proposed method demonstrates a remarkable reduction in power consumption and area, making it a superior choice for energy-efficient and compact digital multiplier designs. These advancements highlight the potential of integrating approximate compressors with the Vedic Urdhva Tiryagbhyam algorithm for high- performance digital arithmetic systems.