HYBRID VLSI ARCHITECTURE FOR HIGH-RESOLUTION IMAGE PROCESSING

Abstract

High-resolution image processing needs have increased in applications that involve medical diagnostics along with satellite imaging and real-time video surveillance and autonomous systems. Real-time operation must be achieved alongside minimum power usage to maintain superior image quality in current programming scenarios. A new VLSI architecture emerges which joins ASIC and FPGA technology advantages to attain optimization of high-resolution image processing operations. The architecture implements two stages of data processing through a combined ASIC and FPGA framework which positions these hardware elements to handle specific computational and adaptive and parallel tasks. The solution method leads to faster processing alongside lower power usage and shorter latency periods along with no reduction in image quality. Experimental testing indicates that the proposed system reaches 60 frames per second (FPS) processing speed coupled with 150 mW power consumption and 20 millisecond latency alongside 180 megapixels per second (MPixels/s) throughput achievement. The proposed approach delivers exceptional image quality performance as shown by PSNR metric of 38.5 dB and SSIM of 0.92. The new proposed structure offers superior performance compared to ASIC-only and FPGA-only and hybrid VLSI designs and emerges as a favorable technology for high-resolution real-time imaging applications.