DESIGN AND IMPLEMENTATION OF PARALLEL PROCESSING FIR FILTER USING MODIFIED BOOTH ENCODING

Abstract

This project presents a Parallel Processing FIR filter or Full Parallel FIR Filter design implemented using the Modified Booth Encoder (MBE) to achieve high-speed performance. A novel hardware architecture employing fine-grained seamless pipelining is proposed, where pipeline registers are strategically placed not only between components but also across them. This ensures minimal gate delays and maximizes throughput. A precise critical path analysis at the gate level enables an optimal pipelining strategy tailored to throughput requirements. The results show that the fully-parallel FIR filter achieves very high throughput with a substantial reduction in area delay product (ADP) compared to existing systolic designs. The proposed design optimizes MBE encoding and parallel processing to achieve significant enhancements in speed, area, and power efficiency. FIR filters are crucial components in digital signal processing applications, but traditional designs often face limitations. The proposed design employs a pipelined architecture, leveraging MBE encoding to reduce computational complexity. This research investigates the potential of parallel processing and MBE encoding in FIR filter design analysing trade-offs between speed, area, and power consumption.